1. Field of the Invention
This invention relates to a high electron mobility field effect transistor and a method for preparation thereof.
2. Description of the Prior Art
In the high electron mobility field effect transistor, referred to hereinafter as HEMT, prepared from a compound semiconductor, such as GaAs, a channel layer and a carrier supplying layer (electron supplying layer) having a band gap width larger than that of the channel layer, are stacked on a wafer, and an electron flowing region occupied by a two-dimensional electron gas is formed in a hetero interface region. The field effect transistor usually has its active region patterned to the shape of an island called mesa and separated by a step difference from the remaining region.
Meanwhile, an AlInAs/GaInAs based HEMT including a AlInAs layer and a GaInAs layer formed on an InP wafer, as disclosed for example in JP Patent KOKOKU Publication No. 2-62945 (1990), has been proposed to taken the place of the proven HEMT employing a GaAs wafer. In an active region of this HEMT, the GaInAs layer acts as channel layer, while the AlInAs layer, stacked thereon, acts as an electron-supplying layer. With such transistor, an electron mobility higher than that with the GaAs/AlGaAs based HEMT may be achieved because of the smaller effective mass of electrons in the GaInAs layer. In such HEMT, the gate electrode is Schottky-connected to the AlInAs layer as the electron supplying layer. Specifically, the gate electrode is formed by vacuum deposition of alloys of Au, Ge or Ni. The source-drain electrodes are connected to the GaInAs layer acting as the channel layer by ohmic connection. More specifically, these electrodes are formed by depositing Pt, Al or W silicides by vacuum deposition or sputtering.
In the above-described HEMT in which the electron supplying layer and the channel layer are deposited in the form of an island, since the gate metallization layer is deposited for being extended on the lateral wall surface of the island-shaped region for providing a gate electrode leadout region, the gate metallization layer is contacted with the exposed surface of the channel layer. With the GaAs/AlGaAs based HEMT, in which the gate metallization layer is formed of an Au-Ti alloy, since the Schottky barrier between the gate metallization layer and the channel layer is as high as about 0.8 eV, the leakage current at the gate electrode presents no serious problem. However, with the HEMT in which the AlInAs layer and the GaInAs layer are stacked to form an island-shaped region, the Schottky barrier between the gate metallization layer and the GaInAs channel layer assumes a lower value of about 0.3 eV. The result is that the leakage current is generated between the gate metallization layer and the channel layer to deteriorate the transistor characteristics.
For overcoming the problem of leakage current, it may be contemplated to provide a sidewall on the lateral wall surface of the island-shaped region to inhibit contact between the gate metallization layer and the channel layer.
It is now assumed that, as shown for example in FIG. 1, an AlInAs layer 2 as a buffer layer is deposited on a semi-insulating InP substrate 1, a GaInAs layer 3 as a channel layer and an n-AlInAs layer 4, as an electron-supplying layer, doped with n-type impurities, are sequentially stacked on this buffer layer, these layers 3, 4 being processed into an island-shaped region 5 for defining an active region 5. An upper surface of the island-shaped region 5 is a gate-forming surface 5a. A sidewall 7 is formed on a lateral wall surface 6 of the island-shaped region 5. The sidewall 7 is formed by etching back a layer of a dielectric material coating at least the island-shaped region 5. However, the etchback end point can be determined only with difficultly such that overetching may be produced depending on the region formed on the wafer so that the upper end face of the sidewall 7 is receded from the gate forming surface 5a. If a gate metallization layer 8 is formed on such wafer, the gate metallization layer 8 tends to creep down on the lateral wall surface 6 in an amount corresponding to the regression of the sidewall 7. Thus it is difficult to stably reduce the leakage current at all times.